Addition operations in a processor either add or subtract representations of numbers. Subsequent to the addition operation, the result of the addition operation, here referred to as a sum, is evaluated to determine whether an overflow has occurred. If an overflow has occurred, the sum is saturated. Saturating means setting to the largest quantity, positive or negative, capable of being represented by the number of bits in the sum. If an overflow occurs in a negative sense, the sum is set to the largest negative number. If an overflow occurs in a positive sense, the sum is set to the largest positive number.
Bit exact standards have been written with single-multiply-accumulate (MAC) processor architectures in mind. Single MAC processors, which typically have one, two-input adder, saturate a sum following each addition operation. For processors requiring the sum of three inputs, a three-input saturation must be performed to be compliant with the bit-exact standards developed for single MAC processors having one two-input adder. To combine three inputs to produce a result, in some combination of addition and subtraction, such as two sequential two-input additions or one three input addition, followed by saturating the result does not assure compliance with bit exact standards developed for single MAC processors having a two-input adder.
One technique to achieve compliance with bit-exact standards in a three-input saturation is to add two of the three inputs, to produce a first sum, saturate the first sum then add the saturated sum to the third input to generate a second sum. Subsequently, the second sum is saturated. This technique has the shortcoming of requiring two sequential addition operations in the critical path of generating the three-input saturated result. What is needed is a technique to generate a three-input saturated result in less time, that is in fewer processor clock cycles, than is required by the two sequential addition operations.